This invention relates generally to semiconductor protection circuitry and more particularly, it relates to a distributed VCC/VSS ESD clamp structure for producing a local and immediate, indirect discharging path so as to prevent inadvertent damage caused by an electrostatic discharge (ESD) or electrical overstress (EOS) event occurring between any two of the external pins of an integrated circuit package when the direct clamp discharging paths are not forming a complete path.
It is generally well-known in the prior art that the magnitude of an electric voltage allowed to be applied to an integrated circuit package is rather limited since the physical size of the integrated circuit package is fairly small and the internal circuitry thereof are tightly packed together with minimum geometries for the merit of performance and integration. When the integrated circuit package is not being used, for example, in storage or handling, the external leads or pins thereof are susceptible to being exposed to a static charge thereon. Such static discharges can be of a catastrophic nature with sufficient energy to cause melting, short circuiting, physical damage, or even destruction of the semiconductor element or chip mounted within the integrated circuit package.
In order to protect the semiconductor chip in the integrated circuit package from being destroyed when such static discharges occur, there has been provided in the prior art ESD protection circuitry which have taken the form of a small diode, a Zener diode, or a transistor connected between either an input pin or an output pin and VCC and VSS power supply pins. These protection circuits break down when the semiconductor chip encounters an unexpectedly high voltage so as to protect the semiconductor chip and to thereby prevent its destruction. However, these prior art protection devices suffer from the drawback that they only offer protection either between the input or output pin and a power supply pin. Thus, in such protection devices, the charges accumulated on either the input pins or the output pins were discharged only when the power supply pin was made to come in contact with the ground potential. Accordingly, the prior art protection devices offer no protection when another input pin or output pin was the one being referenced to ground. Also, no immediate discharge path was provided when the charges were accumulated on a floating power supply pin through an input or output pin.
There has also been provided heretofore power supply clamps, such as VCC/VSS clamp structures, in an attempt to overcome problems associated with the prior art ESD protection circuitry. However, these prior art power supply clamps, either single or multiple, were usually a separate structure that were located at a different part of the semiconductor chip or die, i.e., top, bottom or side peripheral portions thereof. Accordingly, upon the occurrence of an ESD or EOS event, the time constant between the pin on which electrostatic charges are applied (zapped pin) and the power supply clamp may prevent the desired early or timingly discharging through the remote VCC/VSS clamp structure, thereby resulting in an ESD failure.
It would therefore be desirable to provide a VCC/VSS clamp structure which is local to every ESD protection circuitry associated with each of the input and output pins of the integrated circuit package and which is distributed with respect to the bonding pads thereof. This is achieved in the present invention by the provision of local, distributed VCC/VSS clamp structures connected to each ESD structure associated with the input and output pins so as to produce a secondary discharging path in the event that the primary discharging path (through the ESD structure) is incomplete.